Instruction processors of the type known in the art have an instruction set that is primarily implemented in hardware circuitry and microcode instructions. After the design of the processor is embodied within a silicon device, the instruction set is not easily modified without changing the hardware design. That is, additional instructions cannot be readily added to the instruction set. Similarly, the way in which an existing instruction executes cannot be easily changed.
One straightforward way to add an instruction to the instruction set of the processor involves altering the hardware design. For example, decode circuitry within the instruction processor can be modified to decode a previously unused instruction operation code (opcode). This type of modification involves manufacturing a new version of a semiconductor device, which is time consuming and very expensive.
Another mechanism for implementing a less comprehensive change involves modifying microcode instructions. These instructions, which may be stored in one or more Random Access Memories (RAMs) within the instruction processor, are used in conjunction with signals generated in hardware to control the manner in which some, or all, of the instructions execute. To a limited extent, these microcode words can be programmably modified to change the way in which one or more instructions are executed. This could be done, for example, to address a problem that is discovered after the hardware design is completed.
Modifying the microcode stored within an instruction processor allows for design modification without requiring the fabrication of another version of the silicon device. However, this solution is often not viable. For example, it is common for a single set of microcode words to be used to control execution of a group of related instructions. It may be necessary to modify execution of only a single one of these related instructions. In this case, modifying the microcode words will not be possible, since such a modification would undesirably change execution of all other related instructions.
An alternative solution to those described above involves utilizing the operating system of the machine to recognize a newly defined instruction opcode. In most instruction processors, an interrupt is generated to the operating system when an undefined (invalid) instruction opcode is encountered. The operating system will generally recognize this as an error condition. If desired, one of these previously undefined opcodes may be selected to designate a newly defined or modified instruction. When an interrupt is generated to the operating system upon encountering this opcode, the operating system can be used to identify this opcode as a valid instruction. The operating system then emulates the newly defined instruction in software. That is, multiple software instructions are executed to emulate the functions that would otherwise be performed in hardware and/or microcode if the instruction opcode were part of the IP's instruction set.
While the foregoing solution does not require modifying the hardware design, it is relatively inefficient. Interrupt generation and subsequent instruction emulation may require hundreds, if not thousands, of instruction execution cycles to complete. If a frequently executed instruction is implemented in this manner, overall system performance can be significantly impacted by this overhead.
What is needed, therefore, is an improved system and method for making modifications to the hardware instruction set of an instruction processor.